Exploring Design Alternatives Made Easy

Windows

The Diamond Base executable contains all of the design tools and features for you to use Lattice FPGAs from design entry to bitstream download. The supported Windows Operating Systems are Windows 7 (32-bit or 64-bit), Windows 8/8.1 (32-bit or 64-bit) and Windows 10 (32-bit or 64-bit).

Linux

The Diamond Base executable contains all of the design tools and features for you to use Lattice FPGAs from design entry to bitstream download. The supported Linux Operating Systems are Red Hat Enterprise Linux version 4, 5, 6, or 7.

Diamond can be used with either a free license or a subscription license.

Read Licensing FAQ

Diamond Software Free License

Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. The free license enables users to design and evaluate the performance of non-SERDES based Diamond supported devices.

Request a Free License

Diamond Software Subscription License

Design exploration made easy. The full subscription license enables users to design and optimize solutions for all Diamond supported devices, without resorting to workarounds. Implementations can be executed in parallel on multi-core machines to enable you to find the best solution faster.

Request a Subscription License

Device Support by License

Product	Subscription License	Free License
CrossLink
ECP5U
ECP5UM		-
ECP5UM5G		-
LatticeECP3		-
LatticeECP2M/S		-
LatticeECP2S		-
LatticeSC/M		-
MachXO3
MachXO2
MachXO
LatticeXP2
LatticeECP2

• Standard FPGA design flow functions
• Lattice Synthesis Engine (LSE): Lattice developed logic-synthesis tool designed specifically to produce the best possible results for ultra-low density and low density FPGAs (for more information please click here – go to LSE page)
• Intuitive HDL text editor that includes keyword highlight support for VHDL, Verilog HDL, EDIF, and Lattice Preference Language
• IPexpress: an integrated interface to Lattice catalog of functional modules, reference designs, and intellectual property(IP), all optimized for Lattice programmable products
• Netlist Analyzer: an integrated pre and post synthesis result GUI
• LSE editor
• Clarity Designer
• Platform Designer: a tool that enables you to create and control a complete hardware system using the Platform Manager 2 device or MachXO2 with external analog sense and control (ASC)
• Lattice Synthesis Engine (LSE): Lattice developed logic-synthesis tool designed specifically to produce the best possible results for ultra-low density and low density FPGAs (for more information please click here – go to LSE page)
• Spreadsheet View: GUI tool to allow users to enter and view design constraints such as pin assignments, clock resource usage, global preferences, timing preferences and more
• Package View: Easy graphical assignment tool of signals to pins that also allows SSO noise analysis
• Floorplan View to provide the ability to view and edit placement constraints
• Physical View to provide a detailed read-only view of the physical routing of paths for more detailed understanding of timing issues
• Netlist View to provide browsing of design ports, instances, and nets for drag and dropping into other views such as Package View for setting constraints
• NCD View to provide access to detailed usage information of physical components such as SLICEs, PIOs, IOLOGIC, and other elements
• Device View to provide the ability to browse device specific resources and cross-probe to other views
• Cross probing across the views above
• ECO Editor provides quick access to commonly used netlist editing functions such as sysIO settings, PLL parameters, and memory initialization without having to use a full editor such as EPIC
• Multiple implementations in a project to allow multiple versions of a design within a single project for easy design exploration
• Multiple Strategies for implementation “recipes” to be applied to any implementation within a project or shared between projects
• Run Manager view to allow parallel processing of multiple implementations in order to explore design alternatives for the best results
• Timing Analysis View offers an easy to use graphical environment for navigating timing information
• Power Calculator uses highly accurate data models along with a data driven power model to provide power estimation and calculation results, graphical power displays, and reports
• Reveal Inserter uses a signal-centric model that allows easy insertion of embedded logic analyzer debug hardware for real-time analysis
• Reveal Analyzer features the ability to use, multi-event triggering which can be dynamically changed at run-time and an integrated waveform for displaying captured events from the target FPGA
• Simulation Wizard to guide you through all the necessary steps to get your design to a simulator in the format you want
• Fully integrated into Diamond and standalone, Programmer allows easy direct normal programming of single or multiple FPGA devices
• Diamond Deployment Tool provides an intuitive wizard approach to create the appropriate device programming file in the format required by your deployment method
• Tcl Scripting Support
• Third Party Tools: Synopsys Synplify Pro and Aldec Active-HDL Lattice Edition II
• Click here to see an Overview of all Features and Key Concepts related to Diamond

Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. The videos below include an overview of new features in Diamond along with several key improvements and changes in specific areas from earlier software environments. Click on the video links to download an MP4 file which you can then play in your video player of choice.